Voltage shifts and defect-dipoles in ferroelectric capacitors

We review the processes and mechanisms by which voltage offsets occur in the hysteresis loop of ferroelectric materials. Simply stated, voltage shifts arise from near-interfacial charge trapping in the ferroelectric. We show that the impetus behind voltage shifts in ferroelectric capacitors is the net polarization, with the net polarization being determined by the perovskite and the aligned defect-dipole components. Some common defect-dipoles in the PZT system ave lead vacancy-oxygen vacancy complexes. One way to change the net polarization in the ferroelectric is to subject the PZT capacitor to a dc bias at elevated temperature; this process is spectroscopically shown to align defect-dipoles along the direction of the applied electric field. The alignment of defect-dipoles can strongly impact several material properties. One such impact is that it can lead to enhanced voltage shifts (imprint). It is proposed that the net polarization determines the spatial location of the asymmetrically trapped charge that are the cause for the voltage shifts. An enhanced polarization at one electrode interface can lead to larger voltage shifts since it lowers the electrostatic potential well for electron trapping, i.e., more electron trapping can occur. Defect-dipole alignment is also shown to increase the UV sensitivity of the ferroelectric.