%0 Journal Article
%A A.M Dhote
%A S Madhukar
%A W Wei
%A T Venkatesan
%A Ramamoorthy Ramesh
%A C.M Cotell
%B Applied Physics Letters
%D 1996
%G eng
%P 1350-1352
%R 10.1063/1.115931
%T Direct integration of ferroelectric La-Sr-Co-O/Pb-Nb-Zr-Ti-O/La-Sr-Co-O capacitors on silicon with conducting barrier layers
%V 68
%X The growth of a polycrystalline La-Sr-Co-O/Pb-Nb-Zr-Ti-O/La-Sr-Co-O ferroelectric capacitor heterostructure is demonstrated on platinized conducting barrier layers of TiN/poly-Si/Si substrate for integration into high density nonvolatile memory (HDNVM). The concept of conducting bottom layers allows the realization of three-dimensional stacked capacitor-transistor geometry with a direct contact to the memory capacitor, occupying significantly less area on the chip required for HDNVM application. The growth of the ferroelectric heterostructure is achieved at a low temperature of 500-550°C, compatible with existing Si based technology, without losing the structural and phase integrity of the ferroelectric stack and conducting bottom layers. The fatigue-free characteristics up to 1011 cycles at room temperature and 100°C, imprint test and good retaining capability evaluated on these capacitors prove their suitability for HDNVM devices. © 1996 American Institute of Physics.