%0 Journal Article
%K Reliability
%K Deposition
%K Pulsed laser deposition
%K Transmission electron microscopy
%K Crystal growth
%K Ferroelectric materials
%K Ferroelectricity
%K Heterojunctions
%K Ferroelectric capacitors
%K Interfaces (materials)
%K Non-volatile storage
%K Capacitors
%K Semiconducting silicon
%K Low temperature phenomena
%K Conducting barrier stacks
%K High density nonvolatile memory (HDNVM)
%K Low temperature effects
%A A.M Dhote
%A S Madhukar
%A D Young
%A T Venkatesan
%A Ramamoorthy Ramesh
%A C.M Cotell
%A J.M Benedetto
%B Journal of Materials Research
%D 1997
%G eng
%I Materials Research Society
%P 1589-1594
%R 10.1557/JMR.1997.0218
%T Low temperature growth and reliability of ferroelectric memory cell integrated on Si with conducting barrier stack
%V 12
%X Polycrystalline LSCO/PNZT/LSCO ferroelectric capacitor heterostructures were grown by pulsed laser deposition using a composite conducting barrier layer of Pt/TiN on poly-Si/Si substrate. The growth of the ferroelectric heterostructure is accomplished at a temperature in the range of 500-600°C. This integration results in a 3-dimensional stacked capacitor-transistor geometry which is important for high density nonvolatile memory (HDNVM) applications. Transmission electron microscopy shows smooth substrate-film and film-film interfaces without any perceptible interdiffusion. The ferroelectric properties and reliability of these integrated capacitors were studied extensively at room temperature and 100°C for different growth temperatures. The capacitors exhibit excellent reliability, both at room temperature and at elevated temperatures, making them very desirable for HDNVM applications.